View LTC3634-15_8924669.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 for more information www.linear.com/ltc3634 typical a pplica t ion fea t ures descrip t ion 15v dual 3a monolithic step-down regulator for ddr power the lt c ? 3634 is a high efficiency, dual-channel monolithic synchronous step-down regulator which provides power supply and bus termination rails for ddr1, ddr2, and ddr3 sdram controllers. the operating input voltage range is 3.6v to 15v, making it suitable for point-of-load power supply applications from a 5v or 12v input, as well as various battery powered systems. the v tt regulated output voltage is equal to vddqin ? 0.5. an on-chip buffer capable of driving a 10ma load pro - vides a low noise reference output (vttr) also equal to vddqin ? 0.5. the operating frequency is programmable and synchro - nizable from 500khz to 4mhz with an external resistor. the two channels can operate 180 out-of-phase, which relaxes the requirements for input and output capacitance. the unique controlled on-time architecture is ideal for powering ddr applications from a 12v supply at high switching frequencies, allowing the use of smaller external components. the ltc3634 is offered in both 28-pin 4mm 5mm qfn and 28-pin exposed pad tssop packages. efficiency and power loss vs load current a pplica t ions n 3.6v to 15v input voltage range n 3a output current per channel n up to 95% efficiency n selectable 90/180 phase shift between channels n adjustable switching frequency: 500khz to 4mhz n vttr = v ddq /2 = v tt reference n 1.6% accurate vttr at 0.75v n optimal v out range: 0.6v to 3v n 10ma buffered output supplies v ref reference voltage n current mode operation for excellent line and load transient response n external clock synchronization n short-circuit protected n input overvoltage and overtemperature protection n power good status outputs n available in (4mm 5mm) qfn-28 and thermally enhanced 28-lead tssop packages n ddr memory power supplies run1 run2 intv cc phmode mode/sync rt ith1 ith2 ltc3634 3634 ta01a 1.5h 24.3k 12.1k 0.1f 0.01f v ref 0.9v 0.1f pgnd sgnd boost1 sw1 v on1 vddqin v fb1 boost2 sw2 v fb2 v on2 vttr v in1 v in 3.6v to 15v v in2 0.82h 18k 100f 2 v ddq 1.8v/3a 100f 4 v tt 0.9v/3a 910pf 26.4k 324k 560pf 2.2f 47f 2 l , lt, ltc, ltm, linear technology, the linear logo, burst mode and polyphase are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5847554, 6580258, 6476589, 6774611. load current (a) 0 70 80 100 1.5 2.5 3634 ta01b 30 20 0.5 1 2 3 10 60 50 40 0 90 1.4 1.6 2.0 0.6 0.4 0.2 1.2 1.0 0.8 0 1.8 efficiency (%) power loss (w) v in = 12v v ddq v tt (sinking current) v tt (sourcing current) ltc3634 3634fb
2 for more information www.linear.com/ltc3634 a bsolu t e maxi m u m r a t ings v in1 , v in2 ................................................... C0. 3v to 16v v in1 , v in2 transient (note 2) .......................... ............1 8v pgood1, pgood2, v on1 , v on2 ................. C0. 3v to 16v vttr, intv cc , trackss, vddqin .......... C0 .3v to 3.6v ith1, ith2, rt, mode/sync ..... C0 .3v to intv cc + 0.3v v fb1 , v fb2 , phmode .................. C0. 3v to intv cc + 0.3v boost1-sw1, boost2-sw2 .................... C0 .3v to 3.6v boost1, boost2 .................................... C0 .3v to 19.6v run1, run2 .................................... C0 .3v to v in + 0.3v 9 10 top view 29 pgnd ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 pgood1 phmode run1 mode/sync rt run2 sgnd pgood2 v in1 v in1 boost1 intv cc vttr boost2 v in2 v in2 v fb1 trackss ith1 v on1 sw1 sw1 v fb2 vddqin ith2 v on2 sw2 sw2 7 17 18 19 20 21 22 16 8 15 t jmax = 150c, ja = 43c/w exposed pad (pin 29) is pgnd, must be soldered to pcb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view fe package 28-lead plastic tssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ith1 trackss v fb1 pgood1 phmode run1 mode/sync rt run2 sgnd pgood2 v fb2 vddqin ith2 v on1 sw1 sw1 v in1 v in1 boost1 intv cc vttr boost2 v in2 v in2 sw2 sw2 v on2 29 pgnd t jmax = 150c, ja = 25c/w exposed pad (pin 29) is pgnd, must be soldered to pcb p in c on f igura t ion sw source and sink current (dc) (note 3) ................ 3a ope rating junction temperature range (notes 4, 5, 8) ltc3634e, ltc3634i ......................... C40 c to 125c ltc3634h .......................................... C4 0c to 150c ltc3634mp ....................................... C5 5c to 150c storage temperature range .................. C 6 5c to 150c lead temperature (soldering, 10 sec, tssop package) ..................... 260c (note 1) ltc3634 3634fb
3 for more information www.linear.com/ltc3634 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified junction temperature range, otherwise specifications are at t a = 25c (note 4). v in = 12v, intv cc = 3.3v, unless otherwise noted. o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3634eufd#pbf ltc3634eufd#trpbf 3634 28-lead (5mm 4mm) plastic qfn C40c to 125c ltc3634iufd#pbf ltc3634iufd#trpbf 3634 28-lead (5mm 4mm) plastic qfn C40c to 125c ltc3634hufd#pbf ltc3634hufd#trpbf 3634 28-lead (5mm 4mm) plastic qfn C40c to 150c ltc3634mpufd#pbf ltc3634mpufd#trpbf 3634 28-lead (5mm 4mm) plastic qfn C55c to 150c ltc3634efe#pbf ltc3634efe#trpbf ltc3634fe 28-lead plastic tssop C40c to 125c ltc3634ife#pbf ltc3634ife#trpbf ltc3634fe 28-lead plastic tssop C40c to 125c ltc3634hfe#pbf ltc3634hfe#trpbf ltc3634fe 28-lead plastic tssop C40c to 150c ltc3634mpfe#pbf ltc3634mpfe#trpbf ltc3634fe 28-lead plastic tssop C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www .linear .com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ symbol parameter conditions min typ max units v in v in1 , operating supply range v in2 , operating supply range v in1 > 3.6v l l 3.6 1.4 15 15 v v output voltage range v on = v out (note 6) 0.6 3 v i q input dc supply current (v in1 + v in2 ) active (note 7) shutdown run1 = run2 = v in run1 = run2 = 0v 1.3 15 ma a v fbreg1 feedback reference voltage 3.6v < v in < 15v, 0.5v < ith < 1.8v 0c < t a < 85c C55c < t a < 150c l l 0.594 0.592 0.6 0.6 0.606 0.606 v v v fbreg2 feedback reference voltage 3.6v < v in < 15v, 0.5v < ith < 1.8v l vttr C 6 vttr vttr + 6 mv vttr vttr voltage reference 1.5v < vddqin < 2.6v i load = 10ma, c load < 10nf l 0.492 ? vddqin 0.50 ? vddqin 0.508 ? vddqin v i fb feedback pin input current 30 na g m(ea) error amplifier transconductance ith = 1.2v 1.0 ms t on(min) minimum on-time v on = 0.5v, v in = 4v 20 ns t off(min) minimum off-time v in = 6v 40 60 ns f osc oscillator frequency v rt = intv cc r t = 162k r t = 80.6k 1.4 1.7 3.4 2 2 4 2.6 2.3 4.6 mhz mhz mhz i lim1 channel 1 valley switch current limit positive limit negative limit 3.3 4.4 8 5.5 a a i lim2 channel 2 valley switch current limit positive limit negative limit 3.3 4.4 8 5.5 a a r ds(on) channel 1 top switch on-resistance bottom switch on-resistance channel 2 top switch on-resistance bottom switch on-resistance 130 65 130 65 m m m m ltc3634 3634fb
4 for more information www.linear.com/ltc3634 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at t a = 25c (note 4). v in = 12v, intv cc = 3.3v, unless otherwise noted. symbol parameter conditions min typ max units switch leakage current v in = 15v, v run = 0v 0.01 1 a v in overvoltage lockout threshold v in rising v in falling 16.8 15.8 17.5 16.5 18 17 v v intv cc voltage 3.6v < v in < 15v, 0ma load 3.1 3.3 3.5 v intv cc load regulation 0ma to 50ma load, v in = 4v to 15v 0.7 % run threshold rising run threshold falling l l 1.18 0.98 1.22 1.01 1.26 1.04 v v run leakage current 0 1 a pgood good-to-bad threshold v fb rising v fb falling 8 C8 10 C10 % % pgood hysteresis v fb from bad-to-good 15 mv r pgood pgood pull-down resistance 10ma load 15 power good filter time 20 40 s t ss1 channel 1 internal soft-start ramp rate 0.7 1.2 v/ms t ss2 channel 2 internal soft-start ramp rate 1.5 2.2 v/ms v fb1 during tracking trackss = 0.3v 0.28 0.3 0.315 v i trackss trackss pull-up current 1.4 a phase shift between channel 1 and channel 2 phmode = 0v phmode = intv cc 90 180 deg deg phmode threshold voltage v ih v il 1 0.3 v v mode/sync threshold voltage v ih v il 1 0.4 v v sync threshold voltage v ih 0.95 v mode/sync input current mode = 0v mode = intv cc 1.5 C1.5 a a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: t ransient event duration must be < 1% of total lifetime of the part. note 3: guaranteed by long term current density limitations. note 4: the ltc3634 is tested under pulsed load conditions such that t j t a . the ltc3634e is guaranteed to meet specified performance from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3634i is guaranteed to meet specifications over the C40c to 125c operating junction temperature range. the ltc3634h is guaranteed over the C40c to 150c operating junction temperature range and the ltc3634mp is tested and guaranteed over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 5: the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c), package thermal impedance ( ja , in c/w), and power dissipation (p d , in watts) according to the formula: t j = t a + p d ? ja . note 6: output voltage settings above 3v are not optimized for controlled on-time operation. for designs that set output voltages above 3v, please refer to the applications information section for information on device operation outside the optimized range. note 7: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 8: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. ltc3634 3634fb
5 for more information www.linear.com/ltc3634 typical p er f or m ance c harac t eris t ics t a = 25c, v in = 12v, f sw = 1mhz, l = 1.5h unless otherwise noted. efficiency vs load current (burst mode operation) efficiency vs load current (forced continuous) efficiency vs load current (forced continuous) 0.001 efficiency (%) 10 20 10 3634 g01 0 30 40 50 60 70 80 100 90 1 0.01 0.1 load current (a) v out = 1.8v v in = 4v v in = 8v v in = 12v v in = 15v 0.001 efficiency (%) 10 20 10 3634 g02 0 30 40 50 60 70 80 100 90 1 0.01 0.1 load current (a) v in = 4v v in = 8v v in = 12v v in = 15v v out = 1.8v 0.001 efficiency (%) 10 20 10 3634 g03 0 30 40 50 60 70 80 100 90 1 0.01 0.1 load current (a) v out = 1.5v v in = 4v v in = 8v v in = 12v v in = 15v v tt power loss vs load current, sourcing and sinking efficiency vs input voltage reference voltage vs temperature v tt power loss vs load current oscillator frequency vs temperature oscillator internal set frequency vs temperature frequency variation (%) ?8 ?6 ?4 ?2 0 2 4 6 8 3634 g08 ?10 10 temperature (c) ?50 50 150125 25 ?25 0 75 100 frequency (mhz) 1.6 1.8 2.0 2.2 2.4 3634 g09 1.4 2.6 temperature (c) ?50 50 150125 25 ?25 0 75 100 ?3 power loss (w) 3 3634 g04 0 0.2 0.4 0.6 0.8 1.2 1.0 10 2 ?2 ?1 output current (a) v in = 12v v in = 8v v in = 4v v tt = 0.9v l = 0.82h 4 efficiency (%) 16 3634 g05 60 65 70 75 80 90 95 85 1210 14 6 8 input voltage (v) i out = 10ma i out = 100ma i out = 1a i out = 3a ?50 reference voltage (v) 0.597 0.599 50 150 125 3634 g07 0.595 0.601 0.605 0.603 25 ?25 0 75 100 temperature (c) ?3 power loss (w) 3 3634 g06 0 0.2 0.4 0.6 0.8 1.2 1.0 10 2 ?2 ?1 output current (a) v in = 15v v in = 12v v in = 8v v in = 4v v tt = 0.75v l = 0.82h ltc3634 3634fb
6 for more information www.linear.com/ltc3634 valley current positive limit vs temperature valley current negative limit vs temperature trackss pull-up current vs temperature temperature (c) 1.4 1.6 2.0 3634 g15 1.2 1.0 0.8 0.6 1.8 i lim (a) ?50 50 150125 25 ?25 0 75 100 ?50 50 150125 25 ?25 0 75 100 valley current limit (a) 2.5 3.0 3634 g13 2.0 3.5 6.0 4.0 4.5 5.5 5.0 temperature (c) valley current limit (a) ?10 3634 g14 ?11 ?9 ?4 ?8 ?7 ?5 ?6 temperature (c) ?50 50 150125 25 ?25 0 75 100 typical p er f or m ance c harac t eris t ics r ds(on) vs temperature shutdown current vs v in switch leakage vs temperature t a = 25c, v in = 12v, f sw = 1mhz, l = 1.5h unless otherwise noted. ?50 50 150125 25 ?25 0 75 100 r ds(on) (m) 20 40 60 80 100 120 140 3634 g10 0 180 160 temperature (c) top switch bottom switch 4 i q (a) 2 4 6 10 8 16 3634 g11 0 12 20 16 18 14 8 6 10 12 14 v in (v) switch leakage (na) 4000 8000 12000 3634 g12 0 20000 16000 temperature (c) main switch synchronous switch ?50 50 150125 25 ?25 0 75 100 ltc3634 3634fb
7 for more information www.linear.com/ltc3634 typical p er f or m ance c harac t eris t ics load regulation vttr load regulation v ddq load step start-up start-up (channel 2) t a = 25c, v in = 12v, f sw = 1mhz, l = 1.5h unless otherwise noted. v tt load step load current (a) ?3 0.1 0.2 0.3 ?1 1 3634 g16 0 ?0.1 ?2 0 2 3 ?0.2 ?0.3 vttr error (%) vddq v tt vttr load current (ma) ?10 0.1 0.2 ?6 ?2 3634 g17 0 ?0.1 ?8 ?4 0 4 8 2 6 10 ?0.2 vttr error (%) 20s/div 3634 g18 v out 100mv/div ac-coupled i l 2a/div v out = 1.8v i load = 0a to 3a 20s/div 3634 g19 v out 100mv/div ac-coupled i l 2a/div v out = 0.9v i load = ?2a to 2a 200s/div run1 = 5v 3634 g21 v ddq v tt 1v/div run2 5v/div vttr 1v/div v ddq v tt 200s/div 3634 g20 v ddq v tt 1v/div run1 = run2 5v/div vttr 1v/div v ddq v tt ltc3634 3634fb
8 for more information www.linear.com/ltc3634 p in func t ions pgood1 (pin 1/pin 4): channel 1 open-drain power good output pin. pgood1 is pulled to ground when the voltage on the v fb1 pin is not within 8% (typical) of the internal 0.6v reference. this threshold has 15mv of hysteresis. phmode (pin 2/pin 5): phase select input. tie this pin to ground to force both channels to switch 90 out-of-phase. tie this pin to intv cc to force both channels to switch 180 out-of-phase. do not float this pin. run1 (pin 3/pin 6): channel 1 regulator enable pin. enables channel 1 operation by tying run1 above 1.22v. tying it below 1v places channel 1 into shutdown. do not float this pin. mode/sync (pin 4/pin 7): channel 1 mode select and external synchronization input. tie this pin to ground to force continuous synchronous operation on channel 1. floating this pin or tying it to intv cc enables high efficiency burst mode ? operation at light loads. channel 2 operation is forced continuous regardless of the state of this pin. drive this pin with a clock to synchronize the ltc3634 switching frequency. an internal phase-locked loop will force the bottom power nmoss turn-on signal to be synchronized with the rising edge of the clkin signal. when this pin is driven with a clock, forced continuous mode is automatically selected. rt (pin 5/pin 8): oscillator frequency program pin. connect an external resistor (between 80k to 640k) from this pin to sgnd in order to program the frequency from 500khz to 4mhz. when rt is tied to intv cc , the switch- ing frequency will default to 2mhz. see the applications information section. run2 (pin 6/pin 9): channel 2 regulator enable pin. enables channel 2 operation by tying run2 above 1.22v. tying it below 1v places channel 2 into shutdown. do not float this pin. sgnd (pin 7/pin 10): signal ground pin. this pin should have a low noise connection to reference ground. the feedback resistor network, external compensation network, and r t resistor should be connected to this ground. pgood2 (pin 8/pin 11): channel 2 open-drain power good output pin. pgood2 is pulled to ground when the voltage on the v fb2 pin is not within 8% (typical) of vddqin ? 0.5. this threshold has 15mv of hysteresis. v fb2 (pin 9/pin 12): channel 2 output feedback voltage pin. input to the error amplifier that compares the feedback voltage to vttr. connect this pin directly to the output in order to set v out2 equal to vttr. vddqin (pin 10/pin 13): external reference input for channel 2. an internal resistor divider sets the vttr pin voltage to be equal to half the voltage applied to this input. channel 2 uses the vttr pin voltage as its error amplifier reference. ith2 (pin 11/pin 14): channel 2 error amplifier output and switching regulator compensation pin. connect this pin to appropriate external components to compensate the regulator loop frequency response. see the applica - tions information section for guidelines on component selection. v on2 (pin 12/pin 15): on-time voltage input for chan - nel 2. this pin sets the voltage trip point for the on-time comparator. t ying this pin to the output voltage makes the on-time proportional to v out2 when v out2 < 3v. when v out2 > 3v, switching frequency may become higher than the set frequency (see the applications information sec - tion). the pin impedance is nominally 150k. sw2 (pins 13, 14/pins 16, 17): channel 2 switch node connection to external inductor . v oltage swing of sw is from a diode voltage below ground to a diode voltage above v in2 . v in2 (pins 15, 16/pins 18, 19): power supply input for channel 2. input voltage to the on-chip power mosfets on channel 2. this input is capable of operating from a supply voltage separate from v in1 . boost2 (pin 17/pin 20): boosted floating driver supply for channel 2. the (+) terminal of the bootstrap capacitor connects to this pin while the (C) terminal connects to the sw pin. the normal operation voltage swing of this pin ranges from a diode voltage drop below intv cc up to v in2 + intv cc . (qfn/tssop) ltc3634 3634fb
9 for more information www.linear.com/ltc3634 vttr (pin 18/pin 21): reference output. this output is used to supply the v ref voltage for ddr memory. an on- chip buffer amplifier outputs a low noise reference voltage equal to vddqin/2. this output is capable of supplying 10ma. the buffer output can drive capacitive loads up to 0.01f. the error amplifier for channel 2 uses this voltage as its reference voltage. intv cc (pin 19/pin 22): internal 3.3v regulator output. the internal gate drivers and control circuits are powered from this voltage. decouple this pin to power ground with a minimum of 1f low esr ceramic capacitor. the internal regulator is disabled when both channel 1 and channel 2 are disabled with the run1/run2 inputs. boost1 (pin 20/pin 23): boosted floating driver supply for channel 1. the (+) terminal of the bootstrap capacitor connects to this pin while the (C) terminal connects to the sw pin. the normal operation voltage swing of this pin ranges from a diode voltage drop below intv cc up to v in1 + intv cc . v in1 (pins 21, 22/pins 24, 25): power supply input for channel 1. input voltage to the on-chip power mosfets on channel 1. the internal ldo for intv cc is powered from this pin. sw1 (pins 23, 24/pins 26, 27): channel 1 switch node connection to external inductor. voltage swing of sw is from a diode voltage drop below ground to a diode volt - age above v in1 . v on1 (pin 25/pin 28): on-time voltage input for chan - nel 1. this pin sets the voltage trip point for the on-time comparator. t ying this pin to the regulated output voltage makes the on-time proportional to v out1 when v out1 < 3v. when v out1 > 3v, switching frequency may become higher than the set frequency (see the applications information section). the pin impedance is nominally 150k. ith1 (pin 26/pin 1): channel 1 error amplifier output and switching regulator compensation pin. connect this pin to appropriate external components to compensate the regulator loop frequency response. see the applica - tions information section for guidelines on component selection. trackss (pin 27/pin 2): output t racking and soft-start input pin for channel 1. for cing a voltage below 0.6v on this pin bypasses the internal reference input to the error amplifier. the ltc3634 will servo the fb pin to the track voltage. above 0.6v, the tracking function stops and the internal reference resumes control of the error amplifier. an internal 1.4a pull-up current from intv cc allows a soft-start function to be implemented by connecting a capacitor between this pin and sgnd. v fb1 (pin 28/pin 3): channel 1 output feedback voltage pin. input to the error amplifier that compares the feedback voltage to the internal 0.6v reference voltage. connect this pin to a resistor divider network to program the desired output voltage. connecting this pin to intv cc configures the ltc3634 for 2-phase, single output operation; see the applications information section for full discussion. pgnd (exposed pad pin 29/exposed pad pin 29): power ground pin. the (C) terminal of the input bypass capacitor, c in , and the (C) terminal of the output capacitor, c out , should be tied to this pin with a low impedance connec - tion. this pin must be soldered to the pcb to provide a low impedance electrical contact to power ground and good thermal contact to the pcb. p in func t ions (qfn/tssop) ltc3634 3634fb
10 for more information www.linear.com/ltc3634 b lock diagra m 3634 bd + ? switch logic and anti- shoot through r s 3v boost m1 m2 sw pgnd 150k q ? + t on = v von i on i on controller a v = 1 v in v in v on i cmp i rev run i on on 1.22v osc1 channel 1 channel 2 (same as channel 1) + ? intv cc run ? + 0.552v trackss trackss mode/sync vddqin intv cc ? + ? + ? + 0.6v ref 0.648v ov ea uv 1.4a internal soft-start internal soft-start intv cc ? + ? + ov uv mode select 3.3v reg ideal diodes ideal diodes pv in1 burstfc v fb1 osc pll-sync 0.48v at start-up 0.10v after start-up vddqin ? 0.54 vddqin ? 0.46 osc osc1 osc2 phase select + ? ? + vttr v fb2 ith2 pgood2 pgood1 ith1 phmode rt c boost l1 c out c in r2 r1 c ss c vcc c c2 r c2 c c1 r c1 r rt tg bg sense ? sense + ea vddqin ? 0.5 ltc3634 3634fb
11 for more information www.linear.com/ltc3634 o pera t ion the ltc3634 is a dual-channel, current mode monolithic step-down regulator designed to provide high efficiency power conversion for ddr memory supplies and bus ter - mination. its unique controlled on-time architecture allows extremely low step-down ratios while maintaining a fast, constant switching frequency. each channel is enabled by raising the voltage on the run pin above 1.22v nominally. main control loop in normal operation, the internal top power mosfet is turned on for a fixed interval determined by a one-shot timer (on signal in the block diagram). when the top power mosfet turns off, the bottom power mosfet turns on until the current comparator i cmp trips, thus restarting the one-shot timer and initiating the next cycle. inductor current is measured by sensing the voltage drop across the bottom power mosfet. the voltage on the ith pin sets the comparator threshold corresponding to induc - tor valley current. the error amplifier ea adjusts this ith voltage by comparing the feedback signal v fb (derived from the output voltage) to an internal 0.6v reference voltage (channel 1) or the vttr voltage (channel 2). if the load current increases, it causes a drop in the feedback voltage relative to the reference voltage. the ith voltage then rises until the average inductor current matches that of the load current. the switching frequency is determined by the value of the r t resistor, which programs the current for the internal oscillator. an internal phase-locked loop servos the one- shot timer (on signal) such that the internal oscillator edge phase-locks to the sw node edge, thus forcing a constant switching frequency. this unique controlled on-time architecture also allows the switching frequency to be synchronized to an external clock source when it is applied to the mode/sync pin. channel 1 defaults to forced continuous operation once the clock signal is applied (channel 2 is always in forced continuous operation). vttr output buffer the vttr pin outputs a voltage equal to one half of vddqin. it is capable of sourcing/sinking 10ma and driv - ing capacitive loads up to 0.01f. the error amplifier for channel 2 uses this voltage as its reference voltage. high efficiency burst mode operation at light load currents, the inductor current can drop to zero and become negative. in burst mode operation (available only on channel 1), a current reversal comparator (i rev ) detects the negative inductor current and shuts off the bottom power mosfet, resulting in discontinuous opera - tion and increased efficiency. both power mosfets will remain of f until the ith voltage rises above the zero current level to initiate another cycle. during this time, the output capacitor supplies the load current and the part is placed into a low current sleep mode. burst mode operation is disabled by tying the mode/sync pin to ground, which forces continuous synchronous operation regardless of output load current. power good status output the pgood open-drain output will be pulled low if the regulator output exits a 8% window around the regulation point. this threshold has 15mv of hysteresis relative to the v fb pin. to prevent unwanted pgood glitches during transients or dynamic v out changes, the ltc3634 pgood falling edge includes a filter time of approximately 40s. for the v tt output (channel 2), vttr is the regulation point. the pgood2 pin will always be low when the vttr output voltage is less than 300mv. v in overvoltage protection in order to protect the internal power mosfet devices against long transient voltage events, the ltc3634 con - stantly monitors each v in pin for an overvoltage condi - tion. when v in rises above 17.5v, the regulator suspends operation by shutting off both power mosfets on the corresponding channel. once v in drops below 16.5v, the regulator immediately resumes normal operation. the regulator does not execute its soft-start function when exiting an overvoltage condition. out-of-phase operation tying the phmode pin high sets the sw2 falling edge to be 180 out-of-phase with the sw1 falling edge. there is a significant advantage to running both channels out-of- phase. when running the channels in phase, both topside mosfets are on simultaneously, causing large current ltc3634 3634fb
12 for more information www.linear.com/ltc3634 a pplica t ions i n f or m a t ion a general ltc3634 application circuit is shown in figure 1. external component selection is largely driven by the load requirement and switching frequency . component selec - tion typically begins with selecting the feedback resistors to set the desired output voltage. next the inductor l and resistor r t are selected. once the inductor is chosen, the input capacitor (c in ) and the output capacitor (c out ) can be selected. finally, the loop compensation components may be selected to stabilize the step-down regulator. the remaining optional external components can then be se - lected for functions such as loop compensation, trackss, v in , uvlo, and pgood. programming switching frequency selection of the switching frequency is a trade-off between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves efficiency by reducing internal gate charge losses but generally requires larger inductance and capacitance values to maintain low output ripple voltage. connecting a resistor from the rt pin to sgnd programs the switching frequency (f) between 500khz and 4mhz according to the following formula: r rt = 3.2e 11 f where r rt is in and f is in hz. run1 run2 rt intv cc phmode mode/sync ith1 ith2 ltc3634 3634 f01 l1 r2 r1 0.1f c3 0.01f 0.1f pgnd sgnd boost1 sw1 v on1 vddqin v fb1 boost2 sw2 v fb2 v on2 vttr v in1 v in 3.6v to 15v v in2 l2 r comp2 r rt c out1 v ddq c out2 v tt c5 (opt) c comp2 r comp1 c comp1 c2 2.2f c1 c4 (opt) v ref figure 1. typical application circuit for ddr memory supply pulses to be drawn from the input capacitor and supply at the same time. when running the ltc3634 channels out-of-phase, the large current pulses are interleaved, effectively reducing the amount of time the pulses overlap. thus, the total rms input current is decreased, which both relaxes the capacitance requirements for the v in bypass capacitors and reduces the voltage noise on the supply line. one potential disadvantage to this configuration occurs when one channel is operating at 50% duty cycle. in this situation, sw node transitions can potentially couple from one channel to the other, resulting in frequency jitter on one or both channels. this effect can be mitigated with a well designed board layout. alternatively, tying phmode low changes the phase difference to be 90, which may prevent sw1 and sw2 from transitioning at the same point in time. o pera t ion ltc3634 3634fb
13 for more information www.linear.com/ltc3634 figure 3. setting the output voltage a pplica t ions i n f or m a t ion when rt is tied to intv cc , the switching frequency will default to approximately 2mhz, as set by an internal resis - tor. this internal resistor is more sensitive to process and temperature variations than an external resistor (see the t ypical per formance characteristics section) and is best used for applications where switching frequency accuracy is not critical. output v oltage programming each regulators output voltage is set by an external resis - tive divider according to the following equation: v out = v fbreg 1 + r2 r1 ? ? ? ? ? ? where v fbreg is the reference voltage as specified in the electrical characteristics table. the reference voltage is 600mv for channel 1; for channel 2 the reference voltage is equal to the vttr pin voltage. the desired output volt - age is set by appropriate selection of resistors r1 and r2 as shown in figure 3. the buffered output voltage on the vt tr pin is nominally equal to half of the vddqin voltage; thus configuring v out2 as a v tt bus termination supply for ddr memory is as simple as shorting v out2 to v fb2 and connecting vddqin directly to the v out1 (the v ddq supply). choosing large values for r1 and r2 will result in im - proved zero-load efficiency but may lead to undesirable noise coupling or phase margin reduction due to stray capacitances at the v fb node. care should be taken to route the v fb trace away from any noise source, such as the sw trace. the ltc3634 controlled on-time architecture is optimized for an output voltage range of 0.6v to 3v, which is suitable for powering ddr memory. the ltc3634 is capable of regu - lating higher output voltages; however, controlled on-time behavior is not ensured. when the output voltage is greater than 3v , the step-down regulator is for ced to increase the switching frequency in order to achieve output regulation. furthermore, external clock synchronization is no longer possible, and channel 2 cannot maintain 90/180 phase operation with respect to channel 1. in short, the ltc3634 will behave like a constant on-time regulator instead of a controlled on-time regulator. therefore, output voltages greater than 3v should only be used in applications where switching frequency and channel-to-channel phase-locking are not critical performance characteristics. inductor selection for a given input and output voltage, the inductor value and operating frequency determine the inductor ripple current. more specifically, the inductor ripple current decreases with higher inductor value or higher operating frequency according to the following equation: ? i l = v out f ?l ? ? ? ? ? ? 1 ? v out v in ? ? ? ? ? ? where i l = inductor ripple current, f = operating frequency and l = inductor value. a trade-off between component size, efficiency and operating frequency can be seen from this equation. accepting larger values of i l allows the use of lower value inductors but results in greater inductor ltc3634 r2 c f (optional) v out 3634 f03 v fb sgnd r1 figure 2. switching frequency vs r t 0 frequency (khz) 1000 2000 3000 5000 200 700600 3634 f02 0 6000 4000 100 300 400 500 r t resistor (k) ltc3634 3634fb
14 for more information www.linear.com/ltc3634 a pplica t ions i n f or m a t ion core loss, greater esr loss in the output capacitor, and larger output voltage ripple. generally, highest efficiency operation is obtained at low operating frequency with small ripple current. a reasonable starting point is to choose a ripple current somewhere between 600ma and 1.2a peak-to-peak. note that the largest ripple current occurs at the highest v in . exceeding 1.8a is not recommended in order to minimize output voltage ripple. to guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: l = v out f ? ? i l(max) ? ? ? ? ? ? 1 ? v out v in(max) ? ? ? ? ? ? once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire, leading to increased dcr and copper loss. ferrite designs exhibit very low core loss and are pre - ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing satura - tion. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current, so it is important to ensure that the core will not saturate. different core materials and shapes will change the size/cur - rent and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/emi requirements. table 1 gives a sampling of available surface mount inductors. table 1. inductor selection table inductance (h) dcr (m) max current (a) dimensions (mm) height (mm) wrth electronik we-hc 744310 series 0.24 0.55 0.95 1.15 2.00 2.1 3.8 6.4 9.0 14.0 18.0 14.0 11.0 8.5 6.5 7 7 3.3 vishay ihlp-2020bz-01 series 0.22 0.33 0.47 0.68 1 5.2 8.2 8.8 12.4 20 15 12 11.5 10 7 5.2 5.5 2 toko fdv0620 series 0.20 0.47 1.0 4.5 8.3 18.3 12.4 9.0 5.7 7 7.7 2.0 coilcraft d01813h series 0.33 0.56 1.2 4 10 17 10 7.7 5.3 6 8.9 5.0 tdk rlf7030 series 1.0 1.5 8.8 9.6 6.4 6.1 6.9 7.3 3.2 c in and c out selection the input capacitance, c in , is needed to filter the trapezoi - dal wave current at the drain of the top power mosfet. to prevent large voltage transients from occurring, a low esr input capacitor sized for the maximum rms current is recommended. the maximum rms current for a single regulator is given by: i rms = i out(max) v out v in ? v out ( ) v in when both regulators are active, the input current wave - form is significantly different. furthermore, the input rms current varies depending on each outputs load current as well as whether v tt is sinking or sourcing current. ltc3634 3634fb
15 for more information www.linear.com/ltc3634 when sw1 and sw2 operate 180 out-of-phase, the worst-case input rms current occurs when the v tt supply is sinking current and v ddq is sourcing the same amount of current. knowing that v out2 = one-half v out1 in the ddr application, the input rms current in this case is given by: i rms = i out(max) d1 1.5 ? d1 4 ? ? ? ? ? ? for d1 < 0.5 i rms = i out(max) 1 ? 3 4 d1 for d1 > 0.5 where d1 is the duty cycle of channel 1 (v ddq supply). these equations show that maximum i rms occurs at 50% duty cycle (v in = 2 ? v out1 ). this simple worst-case condition may be used for design as deviations in duty cycle do not offer significant relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. even though the ltc3634 design includes an overvoltage protection circuit, care must always be taken to ensure input voltage transients do not pose an overvoltage haz- ard to the part. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response. the output ripple, v out , is approximated by: ? v out < ? i l esr + 1 8 ? f ?c out ? ? ? ? ? ? when using low-esr ceramic capacitors, it is more use - ful to choose the output capacitor value to fulfill a charge a pplica t ions i n f or m a t ion storage requirement. during a load step, the output capaci - tor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. the time required for the feedback loop to respond is dependent on the compensa - tion and the output capacitor size. typically, three to four cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. the output droop, v droop , is usually about three times the linear drop of the first cycle, provided the loop crossover frequency is maximized. thus, a good place to start is with the output capacitor size of approximately: c out 3 ? ? i out f ? v droop though this equation provides a good approximation, more capacitance may be required depending on the duty cycle and load step requirements. the actual v droop should be verified by applying a load step to the output. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are available in small case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, due to the self-resonant and high- q characteristics of some types of ceramic capacitors, care must be taken when these capacitors are used at the input. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the v in input. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. for a more detailed discussion, refer to application note 88. when choosing the input and output ceramic capacitors, choose the x5r and x7r dielectric formulations. these dielectrics have the best temperature and voltage charac - teristics of all the ceramics for a given value and size. ltc3634 3634fb
16 for more information www.linear.com/ltc3634 a pplica t ions i n f or m a t ion choosing compensation components loop compensation is a complicated subject and applica - tion note 76 is recommended reading for a full discussion on maximizing loop bandwidth in a current mode switch - ing regulator. this section will provide a quick method on choosing proper components to compensate the l tc3634 regulators. figure 4 shows the recommended components to be con - nected to the ith pin, and figure 5 shows an approximate bode plot of the buck regulator loop using these compo - nents. it is assumed that the major poles in the system (the output capacitor pole and the error amplifier output pole) are located at a frequency lower than the crossover frequency . figure 4. compensation and filtering components figure 5. bode plot of regulator loop ? p log (?) ? c ? z 3634 f05 ?1 0db |h(s)| ?2 the first step is to choose the crossover frequency f c . higher crossover frequencies will result in a faster loop transient response; however, in order to avoid higher or - der loop dynamics from the switching power stage, it is recommended that f c not exceed one-tenth the switching frequency (f sw ). once f c is chosen, the value of r comp that sets this cross - over frequency can be calculated by the following equation: r comp = 2 ? f c ?c out g m(ea) ? g m(mod) ? ? ? ? ? ? v out v fbreg ? ? ? ? ? ? where g m(ea) is the error amplifier transconductance (see the electrical characteristics section), and g m(mod) is the modulator transconductance (the transfer function from ith voltage to current comparator threshold). for the ltc3634, this transconductance is nominally 7 C1 . once r comp is determined, c comp can be chosen to set the zero frequency (f z ): f z = 1 2 ?c comp ?r comp for 90 of phase margin, f z should be chosen to be less than one-tenth of f c . since the ith node is sensitive to noise coupling, a small bypass capacitor (c byp ) may be used to filter out board noise. however, this cap contributes a pole at f p and may introduce some phase loss at the crossover frequency: f p = 1 2 ?c byp ?r comp for best results, f p should be set high enough such that phase margin is not significantly affected. if necessary, a capacitor c f (as shown in figure 3) may be used to add some phase lead. ltc3634 c byp r comp c comp 3634 f04 ith sgnd ltc3634 3634fb
17 for more information www.linear.com/ltc3634 checking transient response the regulator loop response can be checked by observing the response of the system to a load step. the ith pin not only allows optimization of the control loop behavior but also provides a dc-coupled and ac filtered closed loop response test point. the dc step, rise time, and settling behavior at this test point reflect the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. after choosing compensation values as discussed in the previous section, the design should be tested to verify stability. the component values may be modified slightly to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because their various types and values determine the loop gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of ~1s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out im - mediately shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or discharge c out , generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. when observing the response of v out to a load step, the initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/ dc ratio cannot be used to determine phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to application note 76. a pplica t ions i n f or m a t ion in some applications, a more severe transient can be caused by switching in loads with large (>10f) input capacitors. the discharged input capacitors are effec - tively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap? controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protec - tion, and soft-starting. intv cc regulator bypass capacitor an internal low dropout (ldo) regulator produces the 3.3v supply that powers the internal bias circuitry and drives the gate of the internal mosfet switches. the intv cc pin connects to the output of this regulator and must have a minimum of 1f ceramic bypass capacitance to ground. this capacitor should have low impedance electrical connections to the intv cc and pgnd pins to provide the transient currents required by the ltc3634. this supply is intended only to supply additional dc load currents as desired and not intended to regulate large transient or ac behavior, as this may impact ltc3634 operation. boost capacitor the ltc3634 uses a bootstrap circuit to create a voltage rail above the applied input voltage v in . specifically, a boost capacitor, c boost , is charged to a voltage approximately equal to intv cc each time the bottom power mosfet is turned on. the charge on this capacitor is then used to supply the required transient current during the remainder of the switching cycle. when the top mosfet is turned on, the boost pin voltage will be equal to approximately v in + 3.3v. for most applications, a 0.1f ceramic capacitor closely connected between the boost and sw pins will provide adequate performance. ltc3634 3634fb
18 for more information www.linear.com/ltc3634 a pplica t ions i n f or m a t ion minimum off-time/on-time considerations the minimum off-time is the smallest amount of time that the ltc3634 can turn on the bottom power mosfet, trip the current comparator and turn the power mosfet back off. this time is typically 40ns. for the controlled on-time control architecture, the minimum off-time limit imposes a maximum duty cycle of: dc max = 1C f ? (t off(min) + 2 ? t dead ) where f is the switching frequency, t dead is the nonoverlap time of the switches, or dead time (typically 15ns), and t off(min) is the minimum off-time. if the maximum duty cycle is surpassed, due to a decreasing input voltage for example, the output will drop out of regulation. the minimum input voltage to avoid this dropout condition is: v in(min) = v out 1 ? f ? t off(min) + 2 ? t dead ( ) conversely, the minimum on-time is the smallest dura - tion of time in which the top power mosfet can be in its on state. this time is typically 20ns. in continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of: dc min = (f ? t on(min) ) where t on(min) is the minimum on-time. as the equation shows, reducing the operating frequency will alleviate the minimum duty cycle constraint. when the regulator output is sinking current, the effective minimum on-time of the converter will be increased by the non-overlap time of the power mosfets (or the dead- time) during each sw node transition. this dead-time is nominally 15ns, so when sinking current, the minimum on-time is effectively 15ns + 15ns + 20ns = 50ns. if the minimum on-time constraint is violated, the converter will automatically reduce its own switching frequency in order to maintain output regulation. once the converter reduces its switching frequency, the phase information is lost and the two channels will switch asynchronously. furthermore, the regulator may need to be compensated more conservatively due to the lower switching frequency. mode/sync operation the mode/sync pin is a multipurpose pin allowing both mode selection and operating frequency synchronization. floating this pin or connecting it to intv cc enables burst mode operation on channel 1 for superior efficiency at light load currents at the expense of slightly higher out - put voltage ripple. when the mode/sync pin is tied to ground, forced continuous mode operation is selected, creating the lowest fixed output ripple at the expense of light load efficiency. the l tc3634 will detect the presence of the external clock signal on the mode/sync pin and synchronize the internal oscillator to the phase and frequency of the in - coming clock. the presence of an external clock will place both regulators into forced continuous mode operation. although the r t resistor is not strictly necessary when synchronizing to an external clock, it is recommended to use a r t resistor that matches the nominal external clock frequency in order to keep the switching regulator biased correctly whenever the external clock signal is suddenly removed or reapplied. channel 1 output voltage tracking and soft-start the ltc3634 allows the user to control the output voltage ramp rate of channel 1 by means of the trackss pin. from 0 to 0.6v, the trackss voltage will override the internal 0.6v reference input to the error amplifier, thus regulating the feedback voltage to that of the trackss pin. when trackss is above 0.6v, tracking is disabled and the feedback voltage will regulate to the internal reference voltage. the voltage at the trackss pin may be driven from an external source, or alternatively, the user may leverage the internal 1.4a pull-up current source to implement a soft-start function by connecting an external capacitor (c ss ) from the trackss pin to ground. the relationship between output rise time and trackss capacitance is given by: t ss = 430000 ? c ss ltc3634 3634fb
19 for more information www.linear.com/ltc3634 a default internal soft-start ramp forces a minimum soft- start time of 400s by overriding the trackss pin input during this time period. hence, capacitance values less than approximately 1000pf will not significantly affect soft-start behavior. start-up behavior upon start-up, both channels immediately default to discontinuous operation. channel 1 will remain in dis - continuous burst mode operation until its output rises to greater than 80% of its final value (v fb > 480mv). once the output exceeds this voltage, the operating mode of the regulator switches to the mode selected by the mode/ sync pin as described above. during normal operation, if the output drops below 10% of its final value (as it may when tracking down, for instance), the regulator will automatically switch to burst mode operation to prevent inductor saturation and improve trackss pin accuracy. channel 2 (the v tt termination supply) remains in discon - tinuous operation until its output rises above 300mv, at which point it will automatically switch to forced continu - ous operation. this ensures that the regulator output has a pplica t ions i n f or m a t ion sufficient voltage to discharge the inductor in continuous mode and prevent excessive build-up of energy in the inductor. output power good the pgood output of the ltc3634 is driven by a 15 (typical) open-drain pull-down device. if the output volt - age exits an 8% (typical) regulation window around the target regulation point, the open-drain output will pull down with 15 output resistance to ground, thus dropping the pgood pin voltage. this pull-down device will not shut off until the output re-enters this window and overcomes a small amount of hysteresis. this behavior is described in figure 6. a filter time of 40s (typical) acts to prevent unwanted pgood output changes during v out transient events. as a result, the output voltage must exit the 8% regulation window for 40s before the pgood pin pulls to ground. conversely, the output voltage must be within the target regulation window for 40s before the pgood pin pulls high. figure 6. pgood pin behavior v hys v hys v hys(ch1) : 2.5% v hys(ch2) : ? 100% 3634 f06 output voltage pgood voltage 0% 15mv vttr ?8% nominal output 8% ltc3634 3634fb
20 for more information www.linear.com/ltc3634 a pplica t ions i n f or m a t ion 2-phase, single v tt output configuration the two regulators on the ltc3634 can be easily com - bined to provide a single 2-phase v tt termination supply capable of sourcing and sinking up to 6a. the circuit is shown in figure 7. in this circuit, v fb1 is tied to intv cc to put the ltc3634 into 2-phase operation. when set up for 2-phase operation, the inputs to channel 1s transconductance error amplifier are switched to be the same as channel 2s inputs (v fb2 and vttr), allowing it to be paralleled with channel 2s error amplifier. the ith1 and ith2 pins should be tied together externally to force equal current sharing between both channels. only one compensation network is needed on the ith node, although separate filter caps for each ith pin may be helpful depending on the board layout. in this parallel configuration, it is important to note that the effective g m(ea) and g m(mod) are twice as large as that of a single channel. one advantage to this 2-phase configuration is that both input and output current ripple is significantly reduced compared to a single phase 6a converter solution, because the current waveforms from each regulator are interleaved. refer to application note 77 for a full discussion and analysis on polyphase ? converters. v in1 and v in2 may be powered from separate supply volt - ages (see figure 12). this is useful in cases where power needs to be shared between two different sources. it is important to note that when the v tt output sinks current, it will backfeed through the converter and out of the v in pins. care must be taken to ensure that the input supplies are able to handle this condition. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 +) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in ltc3634 circuits: 1) conduction losses, 2) switching losses and quiescent power loss 3) transition losses and other losses. figure 7. application circuit for a 2-phase, 6a single v tt output run1 run2 rt intv cc phmode v fb1 vddqin ith1 ith2 ltc3634 3634 f07 l1 0.47h 0.1f 0.1f pgnd sgnd boost1 sw1 boost2 sw2 v fb2 v on2 v on1 vttr mode/sync v in1 v in 3.6v to 15v v in2 l2 0.47h r1 160k c out2 100f 4 v tt v ddq /2 at 6a v ref v ddq /2 at 10ma 10pf 6k v ddq supply 1000pf c2 2.2f c1 47f 2 10pf 0.01f ltc3634 3634fb
21 for more information www.linear.com/ltc3634 1. conduction losses are calculated from the dc resis - tances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current flows through inductor l but is chopped between the internal top and bottom power mosfets. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. so to calculate conduction losses: conduction loss = i out 2 (r sw + r l ) 2. the internal ldo supplies the power to the intv cc rail. the total power loss here is the sum of the switching losses and quiescent current losses from the control circuitry. each time a power mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the dc control bias current. in continuous mode, i gatechg = f ? (q t + q b ), where q t and q b are the gate charges of the internal top and bottom power mosfets and f is the switching frequency. for estimation purposes, (q t + q b ) on each ltc3634 regulator channel is approximately 2.3nc. to calculate the total power loss from the ldo load, simply add the gate charge current and quiescent cur - rent and multiply by v in : p ldo = (i gatechg + i q ) ? v in 3. other hidden losses such as transition loss, copper trace resistances, and internal load currents can account for additional efficiency degradations in the overall power system. transition loss arises from the brief amount of time the top power mosfet spends in the saturated region during switch node transitions. the ltc3634 internal power devices switch quickly enough that these losses are not significant compared to other sources. other losses, including diode conduction losses during dead-time and inductor core losses, generally account for less than 2% total additional loss. thermal considerations the ltc3634 requires the exposed package back-plane metal (pgnd) to be well soldered to the pc board to provide good thermal contact. this gives the qfn and tssop packages exceptional thermal properties, which are necessary to prevent excessive self-heating of the part in normal operation. in a majority of applications, the ltc3634 does not dis - sipate much heat due to its high efficiency and low thermal resistance of its exposed-back qfn package. however, in applications where the l tc3634 is running at high ambi - ent temperature, high v in , high switching frequency, and maximum output current load, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 170c, both power switches will be turned off until the temperature returns to 160c. to prevent the ltc3634 from exceeding the maximum junction temperature of 125c, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the tempera - ture rise is given by: t rise = p d ? ja as an example, consider the case when the ltc3634 is used to power ddr2 sdram and is used in an application where maximum ambient temperature is 70c, v in = 12v, frequency = 1mhz, v ddq = 1.8v, v tt = 0.9v, and i load = 2a for both channels. from the r ds(on) graphs in the typical performance characteristics section, the top switch on-resistance is nominally 140m and the bottom switch on-resistance is nominally 75m at 70c ambient. for the v ddq supply, the equivalent power mosfet resistance r sw1 is: r ds(on)top ? 1.8v 12v + r ds(on)bot ? 10.2v 12v = 84.8m the same calculation to the v tt supply (0.9v), yields r sw2 = 79.9m. from the previous sections discussion on gate drive, we estimate the total gate charge current for each regulator to a pplica t ions i n f or m a t ion ltc3634 3634fb
22 for more information www.linear.com/ltc3634 a pplica t ions i n f or m a t ion be 1mhz ? 2.3nc = 2.3ma, and the total i q of both chan - nels is 1.3ma (see the electrical characteristics section). therefore, the total power dissipated by both regulators is: p d = i out1 ( ) 2 ?r sw1 ? ? ? ? ? ? + i out2 ( ) 2 ?r sw2 ? ? ? ? ? ? + v in ? i gatechg + i q ( ) p d = (2a) 2 ? 0.0848 + (2a) 2 ? 0.0799 + 12v ? 2.3ma ? 2 ( ) + 1.3ma ? ? ? ? = 0.730w the qfn 4mm 5mm package junction-to-ambient thermal resistance, ja , is around 43c/w. therefore, the junction temperature of the regulator operating in a 70c ambient temperature is approximately: t j = 0.730w ? 43c/w + 70c = 101c which is below the maximum junction temperature of 125c. with higher ambient temperatures, a heat sink or cooling fan should be considered to drop the junction-to- ambient thermal resistance. alternatively, the exposed pad tssop package may be a better choice for high power applications, since it has better thermal properties than the qfn package. remembering that the above junction temperature is ob - tained from a r ds(on) at 70c, we might recalculate the junction temperature based on a higher r ds(on) since it increases with temperature. redoing the calculation as - suming that r sw increased 12% at 101c yields a new junction temperature of 105c. figure 8 is a temperature derating curve based on the dc1708 demo board (qfn package). it can be used as a guideline to estimate the maximum allowable ambient temperature for given dc load currents in order to avoid exceeding the maximum operating junction temperature of 125c. junction temperature measurement the junction-to-ambient thermal resistance will vary de - pending on the size and amount of heat sinking copper on the pcb board where the part is mounted, as well as the amount of air flow on the device. in order to properly evaluate this thermal resistance, the junction temperature needs to be measured. a clever way to measure the junction figure 8. temperature derating curve for dc1708 demo circuit temperature directly is to use the internal junction diode on one of the pgood pins to measure its diode voltage change based on ambient temperature change. first remove any external passive component on the pgood pin, then pull out 100a from the pgood pin to turn on its internal junction diode and bias the pgood pin to a negative voltage. with no output current load, measure the pgood voltage at an ambient temperature of 25c, 75c and 125c to establish a slope relationship between the voltage on pgood and ambient temperature. once this slope is established, then the junction temperature rise can be measured as a function of power loss in the package with corresponding output load current. although making this measurement with this method does violate absolute maximum voltage ratings on the pgood pin, the applied power is so low that there should be no significant risk of damaging the device. board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3634. check the following in your layout: 1. do the input capacitors connect to the v in and pgnd pins as close as possible? these capacitors provide the ac current to the internal power mosfets and their drivers. 2. the output capacitor, c out , and inductor l should be closely connected to minimize loss. the (C) plate of 0 channel 1 load current (a) 0.5 1.0 1.5 2.0 3.0 2.5 50 125 3634 f08 0 3.5 25 75 100 maximum allowable ambient temperature (c) ch2 load = 0a ch2 load = 1a ch2 load = 2a ch2 load = 3a ltc3634 3634fb
23 for more information www.linear.com/ltc3634 c out should be closely connected to both pgnd and the (C) plate of c in . 3. the resistive divider, (e.g. r1 and r2 in figure 1) must be connected between the (+) plate of c out and a ground line terminated near sgnd. the feedback signal v fb should be routed away from noisy components and traces, such as the sw line, and its trace length should be minimized. in addition, the r t resistor and loop compensation components should be terminated to sgnd. 4. keep sensitive components away from the sw pin. the r t resistor, the compensation components, the feedback resistors, and the intv cc bypass capacitor should all be routed away from the sw trace and the inductor l. 5. a ground plane is preferred, but if not available, the signal and power grounds should be segregated with both connecting to a common, low noise reference point. the connection to the pgnd pin should be made with a minimal resistance trace from the reference point. 6. flood all unused areas on all layers with copper in order to reduce the temperature rise of power components. these copper areas should be connected to the exposed backside of the package (pgnd). refer to figures 10 and 11 for board layout examples. design example as a design example, consider using the ltc3634 (as shown in figure 1) to power ddr2 sdram with the following specifications: v in(max) = 13.2v, i out(max) = 2a, f = 1mhz, v droop(vddq) < 60mv, v droop(vtt ) < 30mv. the following discussion will use equations from the previous sections. first, the correct r t resistor value for 1mhz switching frequency must be chosen. based on previous discus - sions, r t is calculated to be r t = 3.2e 11 f ? ? ? ? ? ? = 320k the closest standard value is 324k. next, select values for r1 and r2 to set channel 1 (v ddq ) to be 1.8v for ddr2 sdram. choosing r1 to be 12.1k, r2 is calculated to be: r2 = 12.1k ? 1.8v 0.6v ? 1 ? ? ? ? ? ? = 24.2k the closest standard value is 24.3k. tying vddqin to v out1 sets v out2 to be half of v out1 . next, we can pick inductor values for both the v ddq and v tt outputs. choosing inductor current ripple to be 1a at maximum v in : l1 = 1.8v 1mhz ?1a ? ? ? ? ? ? 1 ? 1.8v 13.2v ? ? ? ? ? ? = 1.55h l2 = 0.9v 1mhz ?1a ? ? ? ? ? ? 1 ? 0.9v 13.2v ? ? ? ? ? ? = 0.838h standard values of 1.5h and 0.82h should be used. ceramic caps will be used for c out and will be selected based on the charge storage requirement. assuming a worst case 4a load step (C2a to 2a): c out1 3 ? 4a 1mhz ? 60mv = 200f c out2 3 ? 4a 1mhz ? 30mv = 400f lastly, we will choose compensation components. choos - ing the crossover frequency f c = 50khz: r comp1 = 2 ? 50khz ? 200f 1m ? 1 ? 7 ? 1 ? ? ? ? ? ? 1.8v 0.6v ? ? ? ? ? ? = 27k r comp2 = 2 ? 50khz ? 400f 1m ? 1 ? 7 ? 1 ? ? ? ? ? ? 0.9v 0.9v ? ? ? ? ? ? = 18k choosing the zero frequency to be 10khz yields c comp1 = 589pf and c comp2 = 884pf. the closest standard values for the compensation components are 26.7k, 18k, 560pf and 910pf, respectively. the final circuit is shown in figure 9. a pplica t ions i n f or m a t ion ltc3634 3634fb
24 for more information www.linear.com/ltc3634 figure 9. design example circuit a pplica t ions i n f or m a t ion run1 run2 rt intv cc phmode mode/sync ith1 ith2 ltc3634 3634 f09 l1 1.5h 0.1f 0.01f 0.1f r1 12.1k r2 24.3k pgnd sgnd boost1 sw1 v on1 vddqin v fb1 boost2 sw2 v fb2 v on2 vttr v in1 v in 3.6v to 15v v in2 l2 0.82h r3 324k c out2 100f 4 c out1 100f 2 v ddq 1.8v v tt 0.9v v ref 0.9v c5 10pf r comp1 26.7k c comp1 560pf r comp2 18k c comp2 910pf c2 2.2f c1 47f 2 c4 10pf figure 10. example of power component layout for qfn package figure 11. example of power component layout for tssop package sw1 sw2 vias to ground plane vias to ground plane vias to ground plane via to boost2 via to boost1 via to v on2 and v fb2 (not shown) via to v on1 and r2 (not shown) v out2 v out1 sgnd (to nonpower components) 3634 f11 l1 l2 c out2 c out1 c in c in gnd gnd v in c boost1 c boost2 sw2 c boost2 c boost1 sw1 vias to ground plane vias to ground plane vias to ground plane via to boost1 via to boost2 via to v on2 and v fb2 (not shown) via to v on1 /r2 (not shown) v out2 gnd v in gnd v out1 sgnd (to nonpower components) 3634 f10 c out2 c in c in c out1 l2 l1 ltc3634 3634fb
25 for more information www.linear.com/ltc3634 p ackage descrip t ion 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) ltc3634 3634fb
26 for more information www.linear.com/ltc3634 p ackage descrip t ion fe28 (eb) tssop rev j 1012 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 13 14 192022 21 151618 17 9.60 ? 9.80* (.378 ? .386) 4.75 (.187) 2.74 (.108) 28 27 26 2524 23 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.75 (.187) 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev j) exposed pad variation eb ltc3634 3634fb
27 for more information www.linear.com/ltc3634 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 09/13 clarified absolute maximum ratings, added h and mp grades to order information. clarified parametric data. clarified graphs. clarified run1, run2 pin function, intv cc . clarified minimum on-time description. clarified maximum junction temperature in thermal considerations. clarified related parts, added ltc3786 and ltc3633a. 2 3, 4 5, 6 7, 8 18 21 28 b 12/13 clarified dead-time from 10ns to 15ns. 18 ltc3634 3634fb
28 for more information www.linear.com/ltc3634 ? linear technology corporation 2011 lt rev b 1213 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3634 r ela t e d p ar t s typical a pplica t ion part number description comments ltc3633 15v, dual 3a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in(min) = 3.6v, v in(max) = 15v, v out(min) = 0.6v, i q = 500a, i sd <15a, 4mm 5mm qfn-28, tssop-28e package ltc3605 15v, 5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in(min) = 4v, v in(max) = 15v, v out(min) = 0.6v, i q = 2ma, i sd <15a, 4mm 4mm qfn-24 package ltc3604 15v, 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in(min) = 3.6v, v in(max) = 15v, v out(min) = 0.6v, i q = 300a, i sd <15a, 4mm 4mm qfn-20, msop-16e package ltc3603 15v, 2.5a (i out ), 3mhz, synchronous step-down dc/dc converter 95% efficiency, v in(min) = 4.5v, v in(max) = 15v, v out(min) = 0.6v, i q = 75a, i sd <1a, 4mm 4mm qfn-20 msop-16e package ltc3601 15v, 1.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in(min) = 4v, v in(max) = 15v, v out(min) = 0.6v, i q = 300a, i sd <15a, 4mm 4mm qfn-20, msop-16e package ltc3413 5.5v, 3a (i out sink/source), 2mhz, monolithic synchronous regulator for ddr/qdr memory termination 90% efficiency, v in(min) = 2.25v, v in(max) = 5.5v, v out(min) = v ref /2, i q = 280a, i sd <1a, tssop16e package ltc3612 5.5v, 3a, 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in(min) = 2.25v, v in(max) = 5.5v, v out(min) = 0.6v, i q = 75a, i sd <1a, 3mm 4mm qfn-20 tssop-20e package ltc3614 5.5v, 4a, 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in(min) = 2.25v, v in(max) = 5.5v, v out(min) = 0.6v, i q = 75a, i sd <1a, 3mm 5mm qfn-24 package ltc3616 5.5v, 6a, 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in(min) = 2.25v, v in(max) = 5.5v, v out(min) = 0.6v, i q = 75a, i sd <1a, 3mm 5mm qfn-24 package ltc3615 5.5v, dual 3a, 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in(min) = 2.25v, v in(max) = 5.5v, v out(min) = 0.6v, i q = 130a, i sd <1a, 4mm 4mm qfn-24 tssop-24e package ltc3876 38v dual dc/dc controller for ddr power with v tt reference 95% efficiency, v in(min) = 4.5v, v in(max) = 38v, v ppq = 1v to 2.5v, v tt = 1/2 v ppq , 5mm 7mm qfn-38, tssop-38 ltc3633a 20v, dual 3a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in(min) = 3.6v, v in(max) = 20v, i q = 500a, i sd <15a, 4mm 5mm qfn-28, tssop-28e package figure 12a. v tt powered from v ddq figure 12b. 2-phase v tt termination using two input supplies run1 run2 rt intv cc phmode v fb1 vddqin ith1 ith2 ltc3634 3634 ta02b l1 1.5h l2 1.5h 0.1f 0.1f pgnd sgnd boost1 sw1 boost2 sw2 v fb2 v on2 v on1 vttr mode/sync v in2 12v v in1 v tt v ddq /2 at 6a 5v c out2 100f 4 v ref v ddq /2 at 10ma 10k 680pf c2 2.2f c1 22f c3 47f 0.01f 10pf 10pf r1 324k v ddq supply run1 run2 rt intv cc phmode mode/sync ith1 ith2 ltc3634 3634 ta02a l1 1h r2 18.2k r1 12.1k 0.1f 0.1f pgnd sgnd boost1 sw1 v on1 vddqin v fb1 boost2 sw2 v fb2 v on2 vttr v in2 v in 3.6v to 15v v in1 l2 0.47h r comp2 18k c out1 100f 2 v ddq 1.5v c out2 100f 4 c3 0.01f c6 22f v tt 0.75v v ref c comp2 910pf r comp1 26.4k c comp1 560pf c2 2.2f c1 22f c4 10pf c5 10pf r t 162k ltc3634 3634fb

▲Up To Search▲

Price & Availability of LTC3634-15

	To Download LTC3634-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .